EVAL-AD5533EB【PDF 15/16 页】32-Channel Precision Infinite Sample-and

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REV. A

AD5533B

–15–

ISHAs

ACTIVE

LOAD

DRIVER

COMPARATOR

FORMATTER

COMPARE

STORED

DATA

AND INHIBIT

PATTERN

PERIOD

GENERATION

AND

DELAY

TIMING

SYSTEM BUS

ISHA

PARAMETRIC

MEASUREMENT

UNIT

SYSTEM BUS

DUT

ISHA

Figure 13. AD5533B in an ATE System

Typical Application Circuit

The AD5533B can be used to set up voltage levels on 32 channels as

shown in the circuit below. An AD780 provides the 3 V reference

for the AD5533B, and for the AD5541 16-bit DAC. A simple 3-wire

serial interface is used to write to the AD5541. Because the AD5541

has an output resistance of 6.25 k

(typ), the time taken to charge/

discharge the capacitance at the V

pin is significant. Thus an

AD820 is used to buffer the DAC output. Note that it is important

to minimize noise on V

and REFIN when laying out this circuit.

AD5533B

OFFS_IN

OFFS_OUT

REFIN

SCLK

DIN

SYNC

OUT

0–31

AD820

DIN

SCLK

ADDITIONAL PINS OMITTED FOR CLARITY

AD780

OUT

AD5541

REF

Figure 14. Typical Application Circuit

POWER SUPPLY DECOUPLING

In any circuit where accuracy is important, careful consideration

of the power supply and ground return layout helps to ensure

the rated performance. The printed circuit board on which the

AD5533B is mounted should be designed so that the analog

and digital sections are separated and confined to certain areas

of the board. If the AD5533B is in a system where multiple

devices require an AGND-to-DGND connection, the connection

should be made at one point only. The star ground point should

be established as close as possible to the device. For supplies with

multiple pins (V

, V

, AV

) it is recommended to tie those

pins together. The AD5533B should have ample supply bypass-

ing of 10

F in parallel with 0.1

F on each supply located as

close to the package as possible, ideally right up against the device.

The 10

F capacitors are the tantalum bead type. The 0.1

capacitor should have low effective series resistance (ESR) and

effective series inductance (ESI), like the common ceramic types

that provide a low impedance path to ground at high frequencies,

to handle transient currents due to internal logic switching.

The power supply lines of the AD5533B should use as large a trace

as possible to provide low impedance paths and reduce the effects

of glitches on the power supply line. Fast switching signals such

as clocks should be shielded with digital ground to avoid radiating

noise to other parts of the board, and should never be run near

the reference inputs. A ground line routed between the D

and

SCLK lines will help reduce crosstalk between them (not required

on a multilayer board as there will be a separate ground plane,

but separating the lines will help). It is essential to minimize

noise on V

and REFIN lines.

Note it is essential to minimize noise on V

and REFIN lines.

Particularly for optimum ISHA performance, the V

line must

be kept noise-free. Depending on the noise performance of the

board, a noise filtering capacitor may be required on the V

line.

If this capacitor is necessary, then for optimum throughput it may

be necessary to buffer the source that is driving V

. Avoid cross-

over of digital and analog signals. Traces on opposite sides of the

board should run at right angles to each other. This reduces the

effects of feedthrough through the board. A microstrip technique is

by far the best, but not always possible with a double-sided board.

In this technique, the component side of the board is dedicated

to ground plane while signal traces are placed on the solder side.

As is the case for all thin packages, care must be taken to avoid

flexing the CSPBGA package and to avoid a point load on the

surface of this package during the assembly process.

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